Realization of low power, highly linear roic with current mode TDI for long wave infrared detectors

Infrared (IR) imaging systems can be used for variety of civil and military applications such as medical imaging, surveillance, night vision and astronomy applications. In IR systems, readout electronic is a key element between detector and signal processing units. System performance parameters of readout electronic can be enumerated as follows: signal-to-noise ratio (SNR), linearity, input referred noise level and dynamic range. In this thesis, design of a CMOS readout integrated circuit (ROIC) for an array of 6x7 as a part of 576x7 full ROIC system, p-on-n type mercury cadmium telluride (HgCdTe) long wave infrared (LWIR) detectors is presented. AMS 0.35 μ[micro]m, 4-metal 2-poly CMOS process is used in the design of ROIC. Preamplifier of ROIC is direct injection(DI) type due to noise performance. In order to increase SNR, time delay integration (TDI) on 7 detectors is applied with a supersampling rate of three. TDI stage implemented as current mode with current memories rather than capacitances to store integrated charges. This particular novel current mode TDI design in this thesis brings superior features over other topologies like high linearity, low area and very low power consumption in comparison with capacitor based topologies. 99.9% linearity is achieved with 2.5 times smaller area with very low power consumption (28 μ[micro]W per channel) compared to other topologies. ROIC has additional features of bidirectional TDI scanning, programmable five gain settings, and programmable integration time by serial/parallel interface. ROIC operated at 1 MHz with an output dynamic range of 3.75V and input referred noise of 1000 rms electrons

Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays

Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process

Digital pixel readout integrated circuit architectures for LWIR

This paper presents and discusses digital pixel readout integrated circuit architectures for long wavelength infrared (LWIR) in CMOS technology. Presented architectures are designed for scanning and staring arrays type detectors respectively. For scanning arrays, digital time delay integration (TDI) is implemented on 8 pixels with sampling rate up to 3 using CMOS 180nm technology. Input referred noise of ROIC is below 750 rms electron meanwhile power dissipation is appreciably under 30mW. ROIC design is optimized to perform at room as well as cryogenic temperatures. For staring type arrays, a digital pixel architecture relying on coarse quantization with pulse frequency modulation (PFM) and novel approach of extended integration is presented.. It can achieve extreme charge handling capacity of 2.04Ge(-) with 20 bit output resolution and power dissipation below 350 nW in CMOS 90nm technology. Efficient mechanism of measuring the time to estimate the remaining charge on integration capacitor in order to achieve low SNR has employed

Low-power LVDS for digital readout circuits

This paper presents a mixed-signal LVDS driver in 90 nm CMOS technology. The designed LVDS core is to be used as a data link between Infrared Focal Plane Array (IRFPA) detector end and microprocessor input. Parallel data from 220 pixels of IRFPA is serialized by LVDS driver and read out to microprocessor. It also offers a reduced power consumption rate, high data transmission speed and utilizes dense placement of devices for area efficiency. The entire output driver circuit including input buffer draws 5mA while the output swing is 500mV at power supply of 1.2V for data rate of 6.4Gbps. Total LVDS chip area is 0.79 mm(2). Due to these features, the designed LVDS driver is suitable for purposes such as portable, high-speed imaging

Active positive sloped equalizer for x-band SiGe BiCMOS phased array applications

This work presents an active equalizer circuit with positive gain slope at X-Band (8 - 12 GHz). Compared to passive examples, the active equalizer realized better filter and impedance characteristics in frequency of interest with increased functionality for a single amplification stage. It achieved close to 10 dB of peak gain, a + 1.13 dB/GHz gain slope with 2.8 dB NF by utilizing cascode topology. The design reaches a -1.5 dBm input-referred compression point (input-P1dB) while consuming 46 mW of power. To the best of authors’ knowledge, the presented work achieves the best on-chip gain, a gain slope and NF performance in the literature as an equalizer that utilizes SiGe BiCMOS technology

Cryogenic measurements of a digital pixel readout integrated circuit for LWIR

This paper presents and discusses the cryogenic temperature (77K) measurement results of a digital readout integrated circuit (DROIC) for a 32x32 long wavelength infrared pixel sensor array designed in 90nm CMOS process. The chip achieves a signal-to-noise ratio (SNR) of 58dB with a charge handling capacity of 2.03Ge- at cryogenic temperature with 1.3mW of power dissipation. The performance of the readout is discussed in terms of power dissipation, charge handling capacity and SNR considering the fact that the process library models are not optimized for cryogenic temperature operation of the Metal-Oxide-Semiconductor (MOS) devices. These results provide an insight to foresee the design confrontations due to non-optimized device models for cryogenic temperatures particularly for short channel devices

0.13 mu m SiGe BiCMOS w-band low-noise amplifier for passive imaging systems

This paper presents a W-band LNA implemented in 0.13μm SiGe BiCMOS technology. The designed LNA has a peak gain of 20.5dB at 80GHz with a 3-dB bandwidth greater than 25GHz. The simulated noise figure (NF) is lower than 6.2 dB across the entire W-band with a minimum of 5 dB at 93 GHz. The LNA has input P1dB of -16dBm at 94 GHz. The total quiescent DC power consumption of the designed LNA is 16.6mW with a 1.3V supply voltage. Inductors were utilized in matching networks instead of transmission lines to reduce the chip area. The total integrated circuit occupies an area of 0.33 mm2, and the effective chip area is 0.2mm2, excluding the pads. Simulation results indicate that the designed LNA is suitable to be used in a radiometer that has NETD smaller than 0.5 K

A low-power CMOS readout IC with on-chip column-parallel SAR ADCs for microbolometer applications

A readout IC (ROIC) designed for high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The ROIC is designed for higher Ge content SiGe microbolometers which have higher detector resistance (∼1MΩ) and higher TCR values (∼%5.5/K). The ROIC includes column SAR ADCs for on-chip column-parallel analog to digital conversion. SAR ADC architecture is chosen to reduce the overall power consumption. The problem of resistance variation across the bolometers which introduce fixed pattern noise is addressed by setting a tunable reference resistor shared for each column which can be calibrated offline to set the common-mode level. Moreover, column non-uniformity has been reduced through comparator offset compensation in the SAR ADC. The columnwise architecture in this work reduces the number of integrators needed in the architecture and enables 17×17 μm2 pixel sizes. The prototype has been designed and fabricated in 0.25-μm CMOS process

All-pass network and transformer based SiGe BiCMOS phase shifter for multi-band arrays

In this brief, an all-pass network (APN) based SiGe BiCMOS phase shifter (PS) is presented showing a root-meansquare (RMS) phase error lower than 5.6∘ for a 123 % of fractional bandwidth (BW) in a compact area. The APNs, which are designed for equally separated resonance frequencies from the center, are preferred to improve the phase flatness. This results in a low RMS error for a broadened BW. A transformer is utilized to succeed 180∘ phase shift, while the 90∘ of phase state is obtained by a higher-order APN. The bits are cascaded by multiple switches, which are designed for the minimal capacitive parasitic. The custom lumped components are utilized to realize the wideband filters. The presented bidirectional PS guarantee 4-bit of operation for about (5-to-30 GHz) 25 GHz of BW with a maximum 1.2 dB of RMS amplitude error in a 0.45 mm2 area, excluding pads. The presented SiGe BiCMOS passive PS achieved the lowest RMS phase error in a compact area with the widest BW, among its counterparts in the literature